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RF1K49221
Data Sheet August 1999 File Number
4314.1
2.5A, 60V, 0.130 Ohm, ESD Rated, Dual N-Channel LittleFETTM Power MOSFET
The RF1K49221 Dual N-Channel power MOSFET is manufactured using an advanced MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits, gives optimum utilization of silicon, resulting in outstanding performance. It is designed for use in applications such as switching regulators, switching converters, motor drivers, relay drivers, and low voltage bus switches. This device can be operated directly from integrated circuits. The RF1K49221 incorporates ESD protection and is designed to withstand 2kV (Human Body Model) of ESD. Formerly developmental type TA49221.
Features
* 2.5A, 60V * rDS(ON) = 0.130 * 2kV ESD Protected * Temperature Compensating PSPICE(R) Model * Thermal Impedance PSPICE Model * Peak Current vs Pulse Width Curve * UIS Rating Curve * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards"
Symbol
BRAND RF1K49221
S1(1) G1(2) D1(8) D1(7)
Ordering Information
PART NUMBER RF1K49221 PACKAGE MS-012AA
NOTE: When ordering, use the entire part number. For ordering in tape and reel, add the suffix 96 to the part number, i.e. RF1K4922196.
D2(6) D2(5) S2(3) G2(4)
Packaging
JEDEC MS-012AA
BRANDING DASH
5 1 2 3 4
8-136
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. LittleFETTM is a trademark of Intersil Corporation. PSPICE(R) is a registered trademark of MicroSim Corporation. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
RF1K49221
Absolute Maximum Ratings
TA = 25oC Unless Otherwise Specified RF1K49221 60 60 20 2.5 Refer to Peak Current Curve Refer to UIS Curve 2 0.016 2 -55 to 150 300 260 UNITS V V V A
Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (Pulse Width = 5s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrostatic Discharge Rating MIL-STD-883, Category B(2) . . . . . . . . . . . . . . . . . . . . . ESD Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
W W/oC kV oC
oC oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. TJ = 25oC to 125oC.
Electrical Specifications
PARAMETER
TA = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS ID = 250A, VGS = 0V, (Figure 12) VGS = VDS, ID = 250A, (Figure 11) VDS = 60V, TA = 25oC VGS = 0V TA = 150oC VGS = 20V, TA = 25oC VGS = 10V, TA = 85oC ID = 2.5A, (Figures 9, 10) VGS = 10V VGS = 4.5V MIN 60 1 VGS = 0V to 20V VGS = 0V to 10V VGS = 0V to 2V VDD = 48V, ID 2.5A, RL = 19.2 Ig(REF) = 1.0mA (Figure 14) Pulse Width = 1s Device mounted on FR-4 material TYP 10 25 68 32 24 13 0.8 365 140 40 MAX 3 1 50 10 25 0.130 0.350 50 150 29 16 1.0 62.5 UNITS V V A A A A ns ns ns ns ns ns nC nC nC pF pF pF
oC/W
Drain to Source Breakdown Voltage Gate to Source Threshold Voltage Zero Gate Voltage Drain Current
Gate to Source Leakage Current
IGSS
Drain to Source On Resistance
rDS(ON)
Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at 10V Threshold Gate Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction to Ambient
tON td(ON) tr td(OFF) tf tOFF Qg(TOT) Qg(10) Qg(TH) CISS COSS CRSS RJA
VDD = 30V, ID 2.5A, RL = 12, VGS = 10V, RGS = 25, (Figure 14)
VDS = 25V, VGS = 0V, f = 1MHz (Figure 13)
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage Reverse Recovery Time SYMBOL VSD trr TEST CONDITIONS ISD = 2.5A ISD = 2.5A, dISD/dt = 100A/s MIN TYP MAX 1.25 58 UNITS V ns
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RF1K49221 Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 ID, DRAIN CURRENT (A) 3.0 2.5 2.0 1.5 1.0 0.5 0 0 25 50 75 100 125 TA , AMBIENT TEMPERATURE (oC) 150 25 50 75 100 125 150 TA, AMBIENT TEMPERATURE (oC)
0.6 0.4
0.2 0
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs AMBIENT TEMPERATURE
10 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01
THERMAL IMPEDANCE
ZJA, NORMALIZED
1
PDM
0.1 t1 0.01 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x RJA + TA 10-1 100 10-2 t, RECTANGULAR PULSE DURATION (s) 101 102 103
SINGLE PULSE 0.001 10-5 10-4 10-3
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
50
TJ = MAX RATED TA = 25oC IDM, PEAK CURRENT (A)
100
VGS = 20V
ID, DRAIN CURRENT (A)
10
TA = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I
VGS = 10V 10 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION
= I25
150 - TA 125
1
5ms 10ms 100ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1s VDSS(MAX) = 60V 10 DC 100 200
0.1
0.01 0.1
1
1 10-5
10-4
10-3
10-2
10-1
100
101
VDS, DRAIN TO SOURCE VOLTAGE (V)
t, PULSE WIDTH (s)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. PEAK CURRENT CAPABILITY
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RF1K49221 Typical Performance Curves
15 IAS, AVALANCHE CURRENT (A) 10 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
(Continued)
20
VGS = 20V VGS = 10V
ID, DRAIN CURRENT (A)
16
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TA = 25oC VGS = 8V VGS = 7V
12
VGS = 6V
STARTING TJ = 25oC
8 VGS = 5V 4 VGS = 4.5V 0
1 0.1
STARTING TJ = 150oC 1 10 tAV, TIME IN AVALANCHE (ms) 100
0
1.5
3.0
4.5
6.0
7.5
VDS, DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Intersil Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY FIGURE 7. SATURATION CHARACTERISTICS
20 ID(ON), ON-STATE DRAIN CURRENT (A)
rDS(ON), DRAIN TO SOURCE ON RESISTANCE (m)
PULSE TEST PULSE DURATION = 250s DUTY CYCLE = 0.5% MAX
25oC
VDD = 15V
500
PULSE DURATION = 250s, VDD = 15V DUTY CYCLE = 0.5% MAX ID = 5.0A ID = 2.5A
16 -55oC 12 150oC
400
300 ID = 1.25A 200 ID = 0.625A
8
4
100
0 0 2 4 6 8 VGS, GATE TO SOURCE VOLTAGE (V) 10
0 3
4
5
6
7
8
9
10
VGS , GATE TO SOURCE VOLTAGE (V)
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT
2.0 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 250s DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 2.5A 1.5 NORMALIZED GATE THRESHOLD VOLTAGE
1.2 VGS = VDS, ID = 250A
1.0
1.0
0.8
0.5
0.6
0 -80
-40
0
40
80
120
160
0.4 -80
-40
TJ, JUNCTION TEMPERATURE (oC)
0 40 80 120 TJ, JUNCTION TEMPERATURE (oC)
160
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
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RF1K49221 Typical Performance Curves
1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250A 400 1.1 C, CAPACITANCE (pF) CISS
(Continued)
500
300 COSS
1.0
VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS = CDS + CGD
200
0.9
100 CRSS 0.8 -80 0 -40 0 40 80 120 TJ , JUNCTION TEMPERATURE (oC) 160 0 5 10 15 20 VDS , DRAIN TO SOURCE VOLTAGE (V) 25
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
60 VDD = BVDSS 45
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
VDS , DRAIN TO SOURCE VOLTAGE (V)
VDD = BVDSS 7.5
30
15
RL = 24W Ig(REF) = 0.30mA VGS = 10V PLATEAU VOLTAGES IN DESCENDING ORDER: VDD = BVDSS VDD = 0.75 BVDSS VDD = 0.50 BVDSS VDD = 0.25 BVDSS I g ( REF ) 20 ----------------------I g ( ACT ) t, TIME (ms) I g ( REF ) 80 ----------------------I g ( ACT )
5.0
2.5
0
0
NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 14. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT
Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD
+
0V
IAS 0.01
0 tAV
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 16. UNCLAMPED ENERGY WAVEFORMS
8-140
VGS , GATE TO SOURCE VOLTAGE (V)
10.0
RF1K49221 Test Circuits and Waveforms
(Continued)
tON td(ON) RL tr VDS
+
tOFF td(OFF) tf 90%
90%
VGS
0V RGS DUT
0
10% 90%
10%
VGS 0 10%
50% PULSE WIDTH
50%
FIGURE 17. SWITCHING TIME TEST CIRCUIT
FIGURE 18. RESISTIVE SWITCHING WAVEFORMS
VDS RL VDD VDS VGS = 20V VGS
+
Qg(TOT)
Qg(10) VDD VGS VGS = 2V Qg(TH) Ig(REF) VGS = 10V
DUT IG(REF)
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
Soldering Precautions
The soldering process creates a considerable thermal stress on any semiconductor component. The melting temperature of solder is higher than the maximum rated temperature of the device. The amount of time the device is heated to a high temperature should be minimized to assure device reliability. Therefore, the following precautions should always be observed in order to minimize the thermal stress to which the devices are subjected. 1. Always preheat the device. 2. The delta temperature between the preheat and soldering should always be less than 100oC. Failure to preheat the device can result in excessive thermal stress which can damage the device. 3. The maximum temperature gradient should be less than 5oC per second when changing from preheating to soldering. 4. The peak temperature in the soldering process should be at least 30oC higher than the melting point of the solder chosen. 5. The maximum soldering temperature and time must not exceed 260oC for 10 seconds on the leads and case of the device. 6. After soldering is complete, the device should be allowed to cool naturally for at least three minutes, as forced cooling will increase the temperature gradient and may result in latent failure due to mechanical stress. 7. During cooling, mechanical stress or shock should be avoided.
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RF1K49221 PSPICE Electrical Model
SUBCKT RF1K49221 2 1 3 ;
CA 12 8 5.60e-10 CB 15 14 5.30e-10 CIN 6 8 3.40e-10 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DESD1 91 9 DESD1MOD DESD2 91 7 DESD2MOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 67.29 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 1.12e-9 LSOURCE 3 7 4.50e-10 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 28.58e-3 RGATE 9 20 15.34 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RLDRAIN 2 5 10 RLGATE 1 9 11.2 RLSOURCE 3 7 4.5 RSOURCE 8 7 RSOURCEMOD 28.85e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
GATE 1 LGATE LDRAIN DPLCAP 10 RLDRAIN RSLC2 RSLC1 51 + 5 ESLC 51 50 ESG 6 8 + RDRAIN 16 EVTHRES + 19 8 6 MSTRO RIN CIN LSOURCE 8 RSOURCE 7 S1A 12 13 8 S1B 13 CA EGS + 6 8 EDS S2A 15 14 13 S2B CB + 5 8 8 RVTHRES 14 IT SOURCE 3 RLSOURCE RBREAK 17 18 RVTEMP 19 VBAT + 22 21 MMED + EBREAK 17 18 MWEAK DBODY DBREAK 11 5 DRAIN 2
rev 4/8/97
EVTEMP RGATE + 18 9 20 22 DESD1 91 DESD2
RLGATE
VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*30),2.5))} .MODEL DBODYMOD D (IS = 1.95e-13 RS = 2.58e-2 TRS1 = 2.00e-3 TRS2 =-4.39e-7 CJO = 5.15e-10 TT = 5.23e-8 M=0.5) .MODEL DBREAKMOD D (RS = 6.24e-1 TRS1 =-3.03e-4 TRS2 = 4.27e-6 .MODEL DESD1MOD D (BV=32.3 TBV1=0 TBV2=0 RS=0 TRS1=0 TRS2=0 .MODEL DESD2MOD D (BV=32.5 TBV1=0 TBV2=0 RS=25 TRS1=5.18e-4 TRS2=-1.52e-6) .MODEL DPLCAPMOD D (CJO = 1.80e-10 IS = 1e-30 N = 10 M=0.5) .MODEL MMEDMOD NMOS (VTO=2.755 KP=0.21 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=15.34) .MODEL MSTROMOD NMOS (VTO=3.165 KP=3.75 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MWEAKMOD NMOS (VTO=2.520 KP=0.040 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=153.4 RS=0.1) .MODEL RBREAKMOD RES (TC1 = 1.10e-3 TC2 = -1.09e-6) .MODEL RDRAINMOD RES (TC1 = 1.15e-2 TC2 = 4.09e-5 .MODEL RSLCMOD RES (TC1=3.03e-3 TC2=4.52e-6) .MODEL RSOURCEMOD RES (TC1=0 TC2=0) .MODEL RVTHRESMOD RES (TC=-7.20e-4 TC2=-7.11e-6) .MODEL RVTEMPMOD RES (TC1 = -3.01e-3 TC2 = 1.81e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .ENDS NOTE:For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options;IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -7.80 VOFF= -4.80) VON = -4.80 VOFF= -7.80) VON = 1.10 VOFF= 4.10) VON = 4.10 VOFF= 1.10)
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RF1K49221
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
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